Fully Automatic Verifcation and Error Detection for Parameterized Iterative Sequential Circuits

The paper shows how iterative parametric sequential circuits, which are most relevant in practice, can be verified fully automatically. Key observation is that monadic second-order logic on strings provides an adequate level for hardware specification and implementation. This allows us to apply the corresponding decision procedure and counter-model generator implemented in the Mona verification tool, which, for the first time, yields 'push-button' verification, and error detection and diagnosis for the considered class of circuits. As illustrated by means of various versions of counters, this approach captures hierarchical and mixed mode verification, as well as the treatment of varying connectivity in iterative designs.